1. Field of the Invention
The invention pertains generally to computers. In particular, it pertains to managing performance states in computers.
2. Description of the Related Art
In an effort to conserve energy, computer systems have increasingly begun to implement low-power states, in which various techniques are used to reduce power consumption. This is especially true in battery-powered systems, in which reduced power consumption produces increased operational time between battery charges. These power reduction efforts have been targeted at various levels of the computer systems, ranging from the entire system to individual circuits and devices. Various power states have been defined to provide common terminology in power reduction efforts. States S0 through S5 define system level power states, with S0 being fully operational. S1–S5 define non-operational levels of progressively decreasing power consumption and progressively longer times to recover full operation when returning to the S0 state. States D0 through D3 define similar states for devices, such as disk drives, displays, etc., with D0 indicating fully operational and D1–D3 indicating progressively decreasing power consumption and progressively longer times to recover full operation when returning to the D0 state. States C0 through C3 define similar states for the processor, with C0 indicating fully operational. C1 indicates the CPU is halted with a software instruction, and awaits an interrupt to resume processing. C2 stops the clock to the CPU, but permits other devices to communicate with memory by permitting cache snooping operations to continue. C3 prevents even these operations by shutting down the snooping operation and preventing memory communications with other devices. The common factor in these conventional definitions is that there is only one operational state for the system/device/processor that is being regulated. The remaining states are non-operational, with different combinations of power consumption vs. recovery time.
However, various levels of reduced-power reduced-performance can also be defined for the processor, in which the clock speed, voltage level, or both can be changed. These can be considered sub-states of the conventional C0 state. The semiconductor technology that is typically used in a processor consumes much of its power during the state transition of each transistor. Therefore, reducing the clock speed can decrease power consumption by reducing the number of transitions that take place per second. Of course, this also reduces performance, since fewer operations per second can be performed. Power consumption is approximately proportional to clock speed.
Similarly, reducing the voltage level that powers the processor circuitry will reduce the power consumed by the processor. Power consumption is approximately proportional to the square of the voltage level. However, a reduced voltage level also reduces the maximum frequency at which the processor can operate reliably, so reduced voltage can also require a slower clock speed. Thus, these two power-reduction techniques, reduced clock speed and reduced voltage level, must be coordinated to assure that the tradeoff between performance and power savings produces the desired benefits, while avoiding a combination of voltage and clock speed that renders the processor inoperable or unreliable.
Conventional systems have two methods of coordinating the combination of clock speed and voltage level. One involves hard-wiring the selection into platform hardware. This makes it difficult and expensive to change the available combination when new developments make such changes feasible, and retrofitting such changes into existing systems is virtually impossible. The second method is to program the changes into software. However, this makes it easy to program non-optimal or unfeasible frequency/voltage relationships into the system, thus subjecting the system to software design errors and requiring tighter control over the software vendors.